Design and Implementation of Real-Time Transactional Memory

Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is also appealing for real-time systems. In this paper an implementation of real-time transactional memory (RTTM) in the context of a real-time Java chip-multiprocessor (CMP) is presented. To provide a predictable and analyzable solution of transactional memory, the transaction buffer is organized fully associative. Evaluation in an FPGA shows that an associativity of up to 64-way is possible without degrading the overall system performance. The paper presents synthesis results for different RTTM configurations and different number of processor cores in the CMP system. A CMP system with up to 8 processor cores with RTTM support is feasible in an Altera Cyclone-II FPGA.

• Type: Journal
• Year: 2010
• Where: FPL
• Authors: Martin Schoeberl, Peter Hilber
• Keywords: FPL 2010, Hardware, Optimistic Synchronization Mechanism, Real-time Transactional Memory, Transactional Memory