FPL 2010 - PDF Preprint Papers

FPL 2010 International Conference on Field Programmable Logic and Applications

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FPL
2010
Springer

267views Hardware» more FPL 2010»

A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor

13 years 10 months ago

Download www.esa.informatik.tu-darmstadt.de

Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...

Gerald Hempel, Christian Hochberger, Andreas Koch

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Id	Views	Title	Status

1	267	A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor	claim
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7	168	Pipelined FPGA Adders	claim
8	155	Design and Implementation of Real-Time Transactional Memory	claim
9	148	FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators	claim
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11	146	Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs	claim
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13	144	A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs	claim
14	139	Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA	claim
15	134	GPU Versus FPGA for High Productivity Computing	claim
16	133	Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration	claim
17	132	Decision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA	claim
18	131	Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique	claim
19	131	High Density Asynchronous LUT Based on Non-volatile MRAM Technology	claim
20	129	FPGA Implementations of the Round Two SHA-3 Candidates	claim
21	125	Automation Framework for Large-Scale Regular Expression Matching on FPGA	claim
22	124	Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures	claim
23	124	Finding System-Level Information and Analyzing Its Correlation to FPGA Placement	claim
24	112	High-Performance Integer Factoring with Reconfigurable Devices	claim
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26	111	Customized Exposed Datapath Soft-Core Design Flow with Compiler Support	claim
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29	105	Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options	claim
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31	104	Multiplicative Square Root Algorithms for FPGAs	claim
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38	89	FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers	claim
39	85	Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains	claim

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