Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits

This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS gates is compared to that of QFGMOS implementations in a 0.18µm process for different supply voltages and device sizes. A 0.4V VDD full-adder biased for propagation delay similar to that of 0.8V CMOS is

• Type: Conference
• Year: 2005
• Where: IWSOC
• Authors: Kenneth A. Townsend, James W. Haslett, Krzysztof Iniewski
• Keywords: Gate MOS Techniques, Hardware, IWSOC 2005, Simulated Power Consumption, Standard Cmos Gates