The design of a low power asynchronous multiplier

In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low power multipliers: most inputs are positive, and most inputs have a small number of significant bits. These characteristics are exploited in the design of a multiplier that employs three techniques to minimize power consumption: asynchronous control, a radix-2 algorithm, and split registers. The power savings resulting from the use of these techniques are 55%, 23% and 12% respectively when compared to a synchronous multiplier using a radix-4 modified Booth’s algorithm with unified registers. The results are derived from HSPICE simulations using input vectors from benchmark programs. A high-level software model is also used to compare the numbers of transitions in the various models. Categories and Subject Descriptors B.2 [Arithmetic and Logic Structures]: General; B.6 [Logic Design]: Design Styles—Combin...

• Type: Conference
• Year: 2004
• Where: ISLPED
• Authors: Yijun Liu, Stephen B. Furber
• Keywords: ISLPED 2004, Low Power, Low Power Multipliers, Multiplier Operands