Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs

There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumption. In this direction, this paper focuses on a GALS system where the NoC and its end-nodes have independent clocks (unrelated in frequency and phase) and are synchronized via dual-clock FIFOs at network interfaces. Within the network, we assume mesochronous synchronization implemented with hierarchical clock tree distribution. This paper contributes two essential components of any practical design automation support for network instantiation in the target system. On one hand, it introduces a switch design which greatly reduces the overhead for mesochronous synchronization and can be adapted to meet different layout constraints. On the other hand, the paper illustrates a design space exploration framework of mesochronous links that can direct the selection of synchronization options on a portby-port basis for ...

• Type: Conference
• Year: 2010
• Where: DATE
• Authors: Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi
• Keywords: Cost-effective Gals Noc, DATE 2010, Hardware, Mesochronous Synchronization, Relaxed Synchronization Assumption