Design space exploration for minimizing multi-project wafer production cost

- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper1 , we propose a methodology to explore reticle flooplan design space to minimize MPW production cost, facilitated by a new cost model and an efficient reticle floorplanning method. It is shown that a good floorplan saves 47% and 42% production cost with respect to a poor floorplan for small and medium volume production, respectively.

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai
• Keywords: ASPDAC 2006, Chip Fabrication Cost, Floorplan, MPW Production Cost