Design for testability using register-transfer level partial scan selection

Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.

• Type: Conference
• Year: 1995
• Where: ASPDAC
• Authors: Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka
• Keywords: ASPDAC 1995, Hardware, Scan Selection, Scan Selection Technique, Testability Analysis