Designing and testing fault-tolerant techniques for SRAM-based FPGAs

This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable architecture, or they can be implemented at the high-level description, without modification in the FPGA architecture. The high-level method presented in this work is based on Triple Modular Redundancy (TMR) and a combination of Duplication Modular Redundancy (DMR) with Concurrent Error Detection (CED) techniques, which are able to cope with upsets in the combinational and in the sequential logic. The methodology was validated by fault injection experiments in an emulation board. Results have been analyzed in terms of reliability, input and output pin count, area and power dissipation. Categories and Subject Descriptors B.8.1 [Performance and Reliability]: Reliability, Testing, and Fault-Tolerance General Terms Design, Performance, Reliability. Keywords Fault-tolerance, FPGA.

• Type: Conference
• Year: 2004
• Where: CF
• Authors: Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis
• Keywords: CF 2004, Duplication Modular Redundancy, Modular Redundancy, Triple Modular Redundancy