Determination of worst-case aggressor alignment for delay calculation

Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic stages with large complex coupled interconnects. In timing analysis, the worst-case delay of gates along a critical path must include the effect of noise due to switching of nearby aggressor gates. In this paper, we propose a new waveform iteration strategy to compute the delay in the presence of coupling and to align aggressor inputs to determine the worst-case victim delay. We demonstrate the application of our methodology at both the transistor-level and celllevel. In addition, we prove that the waveforms generated in our methodology converge under typical timing analysis conditions.

• Type: Conference
• Year: 1998
• Where: ICCAD
• Authors: Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
• Keywords: Hardware, ICCAD 1998, Timing Analysis, Worst-case Delay, Worst-case Victim Delay