Device and architecture co-optimization for FPGA power reduction

Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer technology. This paper studies the simultaneous evaluation of device and architecture optimization for FPGA. We first develop an efficient yet accurate timing and power evaluation method, called trace-based model. By collecting trace information from cycle-accurate simulation of placed and routed FPGA benchmark circuits and re-using the trace for different Vdd and Vt, we enable the device and architecture co-optimization for hundreds of combinations. Compared to the baseline FPGA which has the architecture same as the commercial FPGA used by Xilinx, and has Vdd suggested by ITRS but Vt optimized by our device optimization, architecture and device co-optimization can reduce energy-delay product by 20.5% without any chip area increase compared to the conventional FPGA architecture. Furthermore, considering power-g...

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
• Keywords: Conventional Fpga Architecture, DAC 2005, Design Automation, Device Optimization, FPGA Benchmark Circuits