Diagnosing multiple transition faults in the absence of timing information

As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such algorithms capable of diagnosing multiple delay faults. One method uses multiple transition fault models and the other reasons with ternary logic values, thus achieving modelindependent diagnosis. Experiments are conducted on ISCAS’85 combinational and full-scan version of ISCAS’89 sequential circuits corrupted with multiple transition faults. The performance of both algorithms are evaluated and compared. The results show good efficiency and diagnostic resolution.

• Type: Conference
• Year: 2005
• Where: GLVLSI
• Authors: Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour
• Keywords: GLVLSI 2005, Multiple Delay Faults, Multiple Transition Faults, Timing Failures Increases, VLSI