Digit-serial/parallel multipliers with improved throughput and latency

––Digit-serial/parallel multipliers with improved throughput and latency are presented. The multipliers are based on unfolded bit-serial/parallel multipliers. The unfolding yields long critical paths that are reduced by splitting the multiplication as a sum of partial multiplications. Using a sum of two partial multiplications yields an increased throughput with between 50 and 120 percent and the latency is reduced with up to 50 percent, compared with the basic digit-serial/parallel multiplier based on unfolding.

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Magnus Karlsson, Mark Vesterbacka
• Keywords: ISCAS 2006, Partial Multiplications, Unfolded Bit-serial/parallel Multipliers, ––Digit-serial/parallel Multipliers