A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression

—A digitally-calibrated technique to suppress the supply voltage sensitivity of a phase-locked loop (PLL) is presented. The voltage-controlled ring oscillator with an additional opposite-supply-sensitivity pair is digitally calibrated to suppress the supply voltage sensitivity. The circuit is fabricated in a 0.18- m CMOS technology and the core area occupies 0.235 mm2. The total power consumption is 16.2 mW for a supply voltage of

• Type: Journal
• Year: 2011
• Where: TVLSI
• Authors: Shih-Yuan Kao, Shen-Iuan Liu
• Keywords: Additional Opposite-supply-sensitivity Pair, Supply Voltage Sensitivity, TVLSI 2011, Voltage-controlled Ring Oscillator