Discovering the input assumptions in specification refinement coverage

14 years 3 months ago

The design of a large chip is typically hierarchical

Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Par

ASPDAC 2006 | Formal Property Verification | Hardware | Level Specific Design | Level Specific Details |

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Added	20 Aug 2010
Updated	20 Aug 2010
Type	Conference
Year	2006
Where	ASPDAC
Authors	Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti

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