The disjunctive decomposition of logic functions

In this paper we present an algorithm for converting a BDD representation of a logic function into a multiple-level netlist of disjoint-support subfunctions. On the theoretical side, we show that the algorithm takes at most quadratic time in the size of the BDD and that the resulting netlist retains the canonicity properties of the original BDD. Experimentally, we found the algorithm to be extremely fast, taking at most a few minutes for the most complex benchmark circuits. The resulting netlist is also often better than what achieved by conventional synthesis tools.

• Type: Conference
• Year: 1997
• Where: ICCAD
• Authors: Valeria Bertacco, Maurizio Damiani
• Keywords: BDD Representation, Hardware, ICCAD 1997, Multiple-level Netlist, Netlist