ICCAD 1997 - PDF Preprint Papers

ICCAD 1997 International Conference on Computer-Aided Design

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ICCAD
1997
IEEE

171views Hardware» more ICCAD 1997»

The disjunctive decomposition of logic functions

14 years 3 months ago

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In this paper we present an algorithm for converting a BDD representation of a logic function into a multiple-level netlist of disjoint-support subfunctions. On the theoretical si...

Valeria Bertacco, Maurizio Damiani

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Id	Views	Title	Status

1	171	The disjunctive decomposition of logic functions	claim
2	162	Application-driven synthesis of core-based systems	claim
3	147	Built-in test generation for synchronous sequential circuits	claim
4	144	Partial scan delay fault testing of asynchronous circuits	claim
5	144	Exploiting off-chip memory access modes in high-level synthesis	claim
6	142	Library-less synthesis for static CMOS combinational logic circuits	claim
7	137	Optimization techniques for high-performance digital circuits	claim
8	134	Post-route optimization for improved yield using a rubber-band wiring model	claim
9	133	Functional simulation using binary decision diagrams	claim
10	131	COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits	claim
11	129	A fast and robust exact algorithm for face embedding	claim
12	127	OPTIMIST: state minimization for optimal 2-level logic implementation	claim
13	126	An output encoding problem and a solution technique	claim
14	125	A deductive technique for diagnosis of bridging faults	claim
15	122	Approximate timing analysis of combinational circuits under the XBD0 model	claim
16	121	Adaptive methods for netlist partitioning	claim
17	118	Global interconnect sizing and spacing with consideration of coupling capacitance	claim
18	117	Decomposition of timed decision tables and its use in presynthesis optimizations	claim
19	117	Generalized matching from theory to application	claim
20	112	Circuit optimization via adjoint Lagrangians	claim
21	108	Negative thinking by incremental problem solving: application to unate covering	claim
22	108	Fault simulation of interconnect opens in digital CMOS circuits	claim
23	106	BIST TPG for faults in system backplanes	claim
24	106	Accurate power estimation for large sequential circuits	claim
25	105	Fast field solver-programs for thermal and electrostatic analysis of microsystem elements	claim
26	103	Delay bounded buffered tree construction for timing driven floorplanning	claim
27	101	Minimum area retiming with equivalent initial states	claim
28	101	NRG: global and detailed placement	claim
29	101	Optimal wire and transistor sizing for circuits with non-tree topology	claim
30	100	Decomposition and technology mapping of speed-independent circuits using Boolean relations	claim
31	99	High-level area and power estimation for VLSI circuits	claim
32	97	Low power logic synthesis for XOR based circuits	claim
33	96	Resource sharing in hierarchical synthesis	claim
34	96	Embedded program timing analysis based on path clustering and architecture classification	claim
35	95	An exact solution to simultaneous technology mapping and linear placement problem	claim
36	94	High-level scheduling model and control synthesis for a broad range of design applications	claim
37	94	PRIMA: passive reduced-order interconnect macromodeling algorithm	claim
38	92	Simulated quenching: a new placement method for module generation	claim
39	91	Interconnect layout optimization under higher-order RLC model	claim
40	90	Efficient coupled noise estimation for on-chip interconnects	claim
41	90	A hierarchical decomposition methodology for multistage clock circuits	claim
42	90	Transformational partitioning for co-design of multiprocessor systems	claim
43	89	Optimal shape function for a bi-directional wire under Elmore delay model	claim
44	87	A new approach to simultaneous buffer insertion and wire sizing	claim
45	86	PHDD: an efficient graph representation for floating point circuit verification	claim
46	86	Interconnect design for deep submicron ICs	claim
47	86	Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems	claim
48	84	Global harmony: coupled noise analysis for full-chip RC interconnect networks	claim
49	83	Replication for logic bipartitioning	claim
50	82	Fast power estimation for deterministic input streams	claim
51	79	An efficient statistical analysis methodology and its application to high-density DRAMs	claim
52	78	A signature based approach to regularity extraction	claim
53	76	Simulation methods for RF integrated circuits	claim
54	75	Scheduling and binding bounds for RT-level symbolic execution	claim
55	75	An exact gate decomposition algorithm for low-power technology mapping	claim
56	71	Timing analysis based on primitive path delay fault identification	claim
57	69	Speeding up technology-independent timing optimization by network partitioning	claim
58	67	Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits	claim
59	66	Sequential optimisation without state space exploration	claim
60	63	Symbolic analysis of large analog circuits with determinant decision diagrams	claim
61	53	A quantitative approach to functional debugging	claim

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