DRG-cache: a data retention gated-ground cache for low power

In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (transistor threshold voltage) process. We utilize the concept of Gated-Ground [5] (NMOS transistor inserted between Ground line and SRAM cell) to achieve reduction in leakage energy without significantly affecting performance. Experimental results on gated-Ground caches show that data is retained (DRG-Cache) even if the memory are put in the stand-by mode of operation. Data is restored when the gated-Ground transistor is turned on. Turning off the gated-Ground transistor in turn gives large reduction in leakage power. This technique requires no extra circuitry; row decoder itself can be used to control the gatedGround transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25? technol...

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Amit Agarwal, Hai Li, Kaushik Roy
• Keywords: DAC 2002, Design Automation, Gated-Ground Transistor, Performance Cache Memories, Transistor Threshold Voltage