DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs

We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within Xilinx’s Virtex-5 FPGAs. An iterative “basic” module outputs a 32 bit column of an AES round each clock cycle, with a

• Type: Conference
• Year: 2008
• Where: FCCM
• Authors: Saar Drimer, Tim Güneysu, Christof Paar
• Keywords: 32 Bit, AES Cipher Implementation, FCCM 2008, Hardware, Xilinx’s Virtex-5 FPGAs