FCCM 2008 - PDF Preprint Papers

FCCM 2008 Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed FCCM-2008 Paper

click to vote

FCCM
2008
IEEE

212views VLSI» more FCCM 2008»

Map-reduce as a Programming Model for Custom Computing Machines

14 years 7 months ago

Download mesl.ucsd.edu

The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...

Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	212	Map-reduce as a Programming Model for Custom Computing Machines	claim
2	205	Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation	claim
3	177	Hardware Scripting in Gel	claim
4	176	The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration	claim
5	165	Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing	claim
6	162	Multiobjective Optimization of FPGA-Based Medical Image Registration	claim
7	160	Facilitating Processor-Based DPR Systems for non-DPR Experts	claim
8	153	A SRAM-based Architecture for Trie-based IP Lookup Using FPGA	claim
9	145	High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves	claim
10	137	Matrix Computations on Heterogeneous Reconfigurable Systems	claim
11	133	Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration	claim
12	133	Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH	claim
13	128	Kiwi: Synthesis of FPGA Circuits from Parallel Programs	claim
14	128	Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems	claim
15	121	FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography	claim
16	118	A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture	claim
17	115	Simultaneous Retiming and Placement for Pipelined Netlists	claim
18	114	Scaling Soft Processor Systems	claim
19	112	Power-Aware and Branch-Aware Word-Length Optimization	claim
20	99	DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers