A DVS-based pipelined reconfigurable instruction memory

Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the total energy. One of the most popular methods to reduce the energy consumption is to shut down idle cache banks. However, we observe that operating idle cache banks at a reduced voltage/frequency level along with the active banks in a pipelined manner can potentially achieve even better energy savings. In this paper, we propose a novel DVS-based pipelined reconfigurable instruction memory hierarchy called PRIM. A canonical example of our proposed PRIM consists of four cache banks. Two of these cache banks can be configured at runtime to operate at lower voltage and frequency levels than that of the normal cache. Instruction fetch throughput is maintained by pipelining the accesses to the low voltage banks. We developed a profiledriven compilation framework that analyzes applications and inserts the appropriat...

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
• Keywords: Appropriate Cache Reconfiguration, DAC 2009, Design Automation, Idle Cache Banks, Instruction Cache