Sciweavers

MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 10 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
ISCAPDCS
2007
14 years 7 days ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi
CASES
2008
ACM
14 years 25 days ago
Efficient code caching to improve performance and energy consumption for java applications
Java applications rely on Just-In-Time (JIT) compilers or adaptive compilers to generate and optimize binary code at runtime to boost performance. In conventional Java Virtual Mac...
Yu Sun, Wei Zhang
CF
2007
ACM
14 years 2 months ago
Performance/area efficiency in chip multiprocessors with micro-caches
This paper proposes the use of very small instruction caches, called micro-caches (
Michela Becchi, Mark A. Franklin, Patrick Crowley
ISCA
1989
IEEE
109views Hardware» more  ISCA 1989»
14 years 2 months ago
Improving Performance of Small On-Chip Instruction Caches
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
Matthew K. Farrens, Andrew R. Pleszkun
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
14 years 3 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
ICCAD
1997
IEEE
162views Hardware» more  ICCAD 1997»
14 years 3 months ago
Application-driven synthesis of core-based systems
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraini...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
14 years 3 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
ISLPED
1999
ACM
150views Hardware» more  ISLPED 1999»
14 years 3 months ago
Using dynamic cache management techniques to reduce energy in a high-performance processor
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. P...
MICRO
2002
IEEE
104views Hardware» more  MICRO 2002»
14 years 3 months ago
Compiling for instruction cache performance on a multithreaded architecture
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
Rakesh Kumar, Dean M. Tullsen