MICRO
2002
IEEE
13 years 10 months ago
2002
IEEE
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
ISCAPDCS
2007
14 years 9 days ago
2007
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
CASES
2008
ACM
14 years 26 days ago
2008
ACM
Java applications rely on Just-In-Time (JIT) compilers or adaptive compilers to generate and optimize binary code at runtime to boost performance. In conventional Java Virtual Mac...
CF
2007
ACM
14 years 2 months ago
2007
ACM
This paper proposes the use of very small instruction caches, called micro-caches (
ISCA
1989
IEEE
14 years 2 months ago
1989
IEEE
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
MICRO
1996
IEEE
14 years 3 months ago
1996
IEEE
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
ICCAD
1997
IEEE
14 years 3 months ago
1997
IEEE
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraini...
MICRO
1999
IEEE
14 years 3 months ago
1999
IEEE
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
ISLPED
1999
ACM
14 years 3 months ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
MICRO
2002
IEEE
14 years 3 months ago
2002
IEEE
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...