Dynamic Voltage and Cache Reconfiguration for Low Power

Given a set of real-time tasks scheduled using the earliest deadline first (EDF) algorithm, we discuss two techniques for reducing power consumption while meeting all timing requirements. Specifically, we proposed a combined Dynamic Voltage Scaling (DVS) and Dynamic Cache Reconfiguration (DCR) technique for low power embedded systems. Toward this goal, we first analyze the potential power savings achievable by each technique (DVS or DCR) alone, then, we present an online algorithm that combines both techniques, reducing the power consumption even more. Our online algorithm gradually constructs a set of pseudo-Pareto-optimal system configurations for each task, which it then uses to determine a low power operating point meeting timing requirements. We evaluate the possible savings and observe that they are highly correlated with the specific timing requirements of the task. We also show that the combination of voltage and cache reconfiguration provides the best overall power savings, a...

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: André C. Nácul, Tony Givargis
• Keywords: DATE 2004, Hardware, Power Consumption, Power Savings, Timing Requirements