DATE 2004 - PDF Preprint Papers

DATE 2004 Automation and Test in Europe Conference and Exhibition Design

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed DATE-2004 Paper

click to vote

DATE
2004
IEEE

210views Hardware» more DATE 2004»

Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow

14 years 4 months ago

Download mesl.ucsd.edu

Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...

Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru N...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	210	Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow	claim
2	185	Energy-Aware System Design for Wireless Multimedia	claim
3	184	Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements	claim
4	181	A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models	claim
5	177	Adaptive Prefetching for Multimedia Applications in Embedded Systems	claim
6	175	Breaking Instance-Independent Symmetries in Exact Graph Coloring	claim
7	174	Graph-Based Functional Test Program Generation for Pipelined Processors	claim
8	173	An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation	claim
9	173	Supporting Cache Coherence in Heterogeneous Multiprocessor Systems	claim
10	168	Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing	claim
11	164	System Design Using Kahn Process Networks: The Compaan/Laura Approach	claim
12	159	Compositional Memory Systems for Data Intensive Applications	claim
13	158	Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits	claim
14	158	Bandwidth-Constrained Mapping of Cores onto NoC Architectures	claim
15	158	Communication Analysis for System-On-Chip Design	claim
16	157	A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning	claim
17	157	Hierarchical Modeling and Simulation of Large Analog Circuits	claim
18	156	Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches	claim
19	154	MultiNoC: A Multiprocessing System Enabled by a Network on Chip	claim
20	154	Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design	claim
21	153	Automatic Generation of Validation Stimuli for Application-Specific Processors	claim
22	153	A Game Theoretic Approach to Low Energy Wireless Video Streaming	claim
23	152	A Design Methodology for the Exploitation of High Level Communication Synthesis	claim
24	151	Boosting: Min-Cut Placement with Improved Signal Delay
25	151	Dynamic Voltage and Cache Reconfiguration for Low Power	claim
26	149	A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation	claim
27	148	MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions	claim
28	147	Automatic Tuning of Two-Level Caches to Embedded Applications	claim
29	147	Formal Refinement and Model Checking of an Echo Cancellation Unit	claim
30	146	Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies	claim
31	146	Analyzing On-Chip Communication in a MPSoC Environment	claim
32	145	Hierarchical Adaptive Dynamic Power Management	claim
33	144	A Framework for Battery-Aware Sensor Management	claim
34	144	Smaller Two-Qubit Circuits for Quantum Communication and Computation	claim
35	144	Cache-Aware Scratchpad Allocation Algorithm	claim
36	143	Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications	claim
37	142	Eliminating False Positives in Crosstalk Noise Analysis	claim
38	141	Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors	claim
39	139	From Synchronous to Asynchronous: An Automatic Approach	claim
40	139	Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays	claim
41	139	Flexible Software Protection Using Hardware/Software Codesign Techniques	claim
42	138	Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors	claim
43	138	STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores	claim
44	138	Microarchitecture Development via Metropolis Successive Platform Refinement	claim
45	136	An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems	claim
46	136	Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases	claim
47	136	Compact Binaries with Code Compression in a Software Dynamic Translator	claim
48	135	Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks	claim
49	135	A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design	claim
50	134	Context-Aware Performance Analysis for Efficient Embedded System Design	claim
51	134	Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding	claim
52	134	Arithmetic Reasoning in DPLL-Based SAT Solving	claim
53	134	Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor	claim
54	133	Channel Decoder Architecture for 3G Mobile Wireless Terminals	claim
55	133	Model-Based Specification and Execution of Embedded Real-Time Systems	claim
56	132	LZW-Based Code Compression for VLIW Embedded Systems	claim
57	132	Hybrid Architectural Dynamic Thermal Management	claim
58	131	Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures	claim
59	131	Testing of Quantum Dot Cellular Automata Based Designs	claim
60	130	Dynamic Power Management Using Data Buffers	claim
61	130	Utilizing Formal Assertions for System Design of Network Processors	claim
62	130	Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology	claim
63	130	Thermal and Power Integrity Based Power/Ground Networks Optimization	claim
64	129	Improving Design and Verification Productivity with VHDL-200x	claim
65	129	Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach	claim
66	129	On the Design and Verification Methodology of the Look-Aside Interface	claim
67	129	Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach	claim
68	128	Enhanced Diameter Bounding via Structural	claim
69	128	A Crosstalk Aware Interconnect with Variable Cycle Transmission	claim
70	128	An Assembler Driven Verification Methodology (ADVM)	claim
71	128	Synthesis for Manufacturability: A Sanity Check	claim
72	127	Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA	claim
73	126	GRAAL - A Development Framework for Embedded Graphics Accelerators	claim
74	126	Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures	claim
75	126	Low Static-Power Frequent-Value Data Caches	claim
76	125	Fast Comparisons of Circuit Implementations	claim
77	125	Extremely Low-Power Logic	claim
78	125	Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance	claim
79	123	On Concurrent Error Detection with Bounded Latency in FSMs	claim
80	123	Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies	claim
81	122	Phase Coupled Code Generation for DSPs Using a Genetic Algorithm	claim
82	121	Experiences during the Experimental Validation of the Time-Triggered Architecture	claim
83	121	Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models	claim
84	120	Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study	claim
85	120	Direct Nonlinear Order Reduction with Variational Analysis	claim
86	120	Pattern Selection for Testing of Deep Sub-Micron Timing Defects	claim
87	120	Evaluation of SystemC Modelling of Reconfigurable Embedded Systems	claim
88	119	Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms	claim
89	119	MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor	claim
90	119	Net and Pin Distribution for 3D Package Global Routing	claim
91	119	Using a Victim Buffer in an Application-Specific Memory Hierarchy	claim
92	118	Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals	claim
93	118	SCORE: SPICE COmpatible Reluctance Extraction	claim
94	118	Distributed Multimedia System Design: A Holistic Perspective	claim
95	117	Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks	claim
96	116	OCCN: A Network-On-Chip Modeling and Simulation Framework	claim
97	116	A Novel SAT All-Solutions Solver for Efficient Preimage Computation	claim
98	116	Full-Chip Multilevel Routing for Power and Signal Integrity	claim
99	115	Aspects of Formal and Graphical Design of a Bus System	claim
100	114	Synthesis of Reversible Logic	claim
101	114	Scheduling Reusable Instructions for Power Reduction	claim
102	114	Workload Characterization Model for Tasks with Variable Execution Demand	claim
103	114	Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks	claim
104	113	Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications	claim
105	113	Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method	claim
106	111	State-Preserving vs. Non-State-Preserving Leakage Control in Caches	claim
107	110	Interactive Cosimulation with Partial Evaluation	claim
108	109	Using Counter Example Guided Abstraction Refinement to Find Complex Bugs	claim
109	109	RTL Processor Synthesis for Architecture Exploration and Implementation	claim
110	108	Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures	claim
111	108	Poor Man's TBR: A Simple Model Reduction Scheme	claim
112	107	A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms	claim
113	107	Profile Guided Management of Code Partitions for Embedded Systems	claim
114	106	Realizable Reduction for Electromagnetically Coupled RLMC Interconnects	claim
115	106	A Self-Tuning Cache Architecture for Embedded Systems	claim
116	105	Time-Energy Design Space Exploration for Multi-Layer Memory Architectures	claim
117	103	A Novel Implementation of Tile-Based Address Mapping	claim
118	102	High Security Smartcards	claim
119	97	A Formal Verification Methodology for Checking Data Integrity	claim
120	92	Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming	claim
121	89	Improved Symoblic Simulation by Dynamic Funtional Space Partitioning	claim
122	82	Managing Don't Cares in Boolean Satisfiability	claim
123	80	Random Jitter Extraction Technique in a Multi-Gigahertz Signal	claim
124	79	Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers