Effects of on-chip inductance on power distribution grid

With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. Minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids.; B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids. General Terms Performance, ...

• Type: Conference
• Year: 2005
• Where: ISPD
• Authors: Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
• Keywords: Hardware, ISPD 2005, On-chip Decoupling Capacitance, On-chip Inductance, Power Supply Noise