Efficient ASIP design for configurable processors with fine-grained resource sharing

Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. In this paper, we investigate two techniques to improve these flows, so that ASIP can be efficiently applied to simple computer architectures in embedded applications. Firstly, we efficiently generate custom instructions with multi-cycle IO (which allows multi-outputs), thus removing the constraint imposed by the ports of the register file. Secondly, we allow identical portions of different custom instructions to be shared, thus allowing more custom instructions under the same area constraint. To handle the greatly increased exploration space, we propose several heuristics to keep the problem tractable. Experimental results show that we can achieve 3x speedup in some cases. Categories and Subject Descriptors B.7.2 [Hardware]: INTEGRATED CIRCUITS

• Type: Conference
• Year: 2008
• Where: FPGA
• Authors: Quang Dinh, Deming Chen, Martin D. F. Wong
• Keywords: Application-Specific Instruction-set Processors, Custom Instructions, Design Automation Flows, FPGA, FPGA 2008