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    VLSID
    1995
    IEEE
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    An efficient automatic test generation system for path delay faults in combinational circuits

    14 years 3 months ago
    An efficient automatic test generation system for path delay faults in combinational circuits
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    Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi
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    Added 26 Aug 2010
    Updated 26 Aug 2010
    Type Conference
    Year 1995
    Where VLSID
    Authors Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
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