Efficient checker processor design

The design and implementation of a modern microprocessor creates many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. In our previous work, we proposed a solution to these problems by adding a simple, easily verifiable checker processor at pipeline retirement. Performance analyses of our initial design were promising, overall slowdowns due to checker processor hazards were less than 3%. However, slowdowns for some outlier programs were larger. In this paper, we examine closely the operation of the checker processor. We identify the specific reasons why the initial design works well for some programs, but slows others. Our analyses suggest a variety of improvements to the checker processor storage system. Through the addition of a 4k checker cache and eight entry store queue, our optimized design eliminates virtually all core processor slowd...

• Type: Conference
• Year: 2000
• Where: MICRO
• Authors: Saugata Chatterjee, Christopher T. Weaver, Todd M. Austin
• Keywords: Checker Processor, Checker Processor Storage, Hardware, MICRO 2000, Verifiable Checker Processor