MICRO 2000 - PDF Preprint Papers

MICRO 2000 IEEE/ACM International Symposium on Microarchitecture

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed MICRO-2000 Paper

click to vote

MICRO
2000
IEEE

176views Hardware» more MICRO 2000»

An Advanced Optimizer for the IA-64 Architecture

14 years 6 days ago

Download www.info.uni-karlsruhe.de

level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...

Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	176	An Advanced Optimizer for the IA-64 Architecture	claim
2	162	Accurate and efficient predicate analysis with binary decision diagrams	claim
3	137	Relational profiling: enabling thread-level parallelism in virtual machines	claim
4	133	Compiler controlled value prediction using branch predictor based confidence	claim
5	129	Architectural Considerations for CPU and Network Interface Integration	claim
6	124	Calpa: a tool for automating selective dynamic compilation	claim
7	122	Dynamic zero compression for cache energy reduction	claim
8	122	An Integrated Environment for Teaching Computer Architecture	claim
9	121	Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures	claim
10	120	The Broadband Revolution	claim
11	118	A study of slipstream processors	claim
12	112	Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors	claim
13	112	The MAJC Architecture: A Synthesis of Parallelism and Scalability	claim
14	111	The TigerSHARC DSP Architecture	claim
15	108	High Availability and Reliability in the Itanium Processor	claim
16	107	Register integration: a simple and efficient implementation of squash reuse	claim
17	107	An integrated approach to accelerate data and predicate computations in hyperblocks	claim
18	107	Aggressive Business Tactics: Are There Limits?	claim
19	107	Interaction Design	claim
20	98	Efficient conditional operations for data-parallel architectures	claim
21	98	The store-load address table and speculative register promotion	claim
22	97	IP-Related Refusals to Deal-Part 2: Pretext and Misconduct as Standards	claim
23	96	Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors	claim
24	95	Very low power pipelines using significance compression	claim
25	95	A Single-Chip Multiprocessor for Smart Terminals	claim
26	95	Predicting the Future	claim
27	95	Doing it right	claim
28	94	Napster: A Walking Copyright Infringement?	claim
29	92	Windows 2000	claim
30	90	Eager writeback - a technique for improving bandwidth utilization	claim
31	90	Happy New Year	claim
32	88	Two-level hierarchical register file organization for VLIW processors	claim
33	86	On pipelining dynamic instruction scheduling logic	claim
34	84	The impact of delay on the design of branch predictors	claim
35	84	The Good, the Bad, and the Ugly	claim
36	82	Connecting the Home With a Phone Line Network Chip Set	claim
37	81	A static power model for architects	claim
38	80	Silent stores for free	claim
39	80	Xtensa: A Configurable and Extensible Processor	claim
40	75	The Stanford Hydra CMP	claim
41	74	Predictor-directed stream buffers	claim
42	74	A framework for dynamic energy efficiency and temperature management	claim
43	72	PipeRench implementation of the instruction path coprocessor	claim
44	72	Microprocessors, Microcontrollers, and Systems in the New Millennium	claim
45	71	Improving BTB performance in the presence of DLLs	claim
46	69	Falling Through the Cracks at Microsoft	claim
47	68	Efficient checker processor design	claim
48	68	Performance improvement with circuit-level speculation	claim
49	67	Modulo scheduling for a fully-distributed clustered VLIW architecture	claim
50	66	A Revolution? How Do You Know?	claim
51	61	Reducing wire delay penalty through value prediction	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers