Efficient digit-serial FIR filters with skew-tolerant domino

A novel connection between digit-serialcomputationand skew-tolerant domino circuit design is exploited to create very efficient implementations of FIR digital filters. In our approach, a digit size of N bits is mapped onto an N-phase overlapping clocking scheme in such a way that N bits are processed in each full clock cycle. In addition, a VHDLbased verification strategy is used to capture the essential time-borrowing behavior of skew-tolerant domino circuits in an accurate and efficient manner. The simulation results show that an 8-tap digit-serial FIR filter constructed with skew-tolerant domino is up to 36% faster than one built using traditional domino circuits.

• Type: Conference
• Year: 2002
• Where: ISCAS
• Authors: Sungwook Kim, Gerald E. Sobelman
• Keywords: Digit-serialcomputationand Skew-tolerant Domino, Domino Circuits, Hardware, ISCAS 2002, Skew-tolerant Domino Circuits