An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation

In this paper, we present an efficient hardware architecture for real-time implementation of quarter-pixel accurate variable block size motion estimation for H.264 / MPEG4 Part 10 video coding. The proposed hardware performs quarter-pixel interpolation dynamically, i.e. only the quarter pixels necessary for performing quarter-pixel accurate search at the location pointed by the half-pixel motion vector are calculated. This reduces the amount of computation performed for quarter-pixel interpolation, and therefore reduces the power consumption of the quarter-pixel accurate motion estimation hardware. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed hardware architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 60 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 34 VGA frames (640x480) per second.

• Type: Conference
• Year: 2007
• Where: DSD
• Authors: Serkan Oktem, Ilker Hamzaoglu
• Keywords: DSD 2007, Hardware, Hardware Architecture, Motion Estimation