An Efficient Mechanism for Performance Optimization of Variable-Latency Designs

In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case conditions could lead to inefficient resource use. It is possible to improve the throughput of such circuits by introducing variable latency. One of the existing realizations of variable-latency design style is based on Telescopic Units. The design of the hold logic in telescopic units influences the circuit's throughput. In this paper, we show that the traditionally-designed hold logic in telescopic units may be inaccurate. We make use of the short path activation conditions to obtain more accurate hold logic than that commonly applied in the telescopic units. On average, our approach achieves a performance gain of 25.79% compared to 14.04%, which was reported in the previous works. Categories and Subject Descriptors: B.6.3 [Hardware]: Logic design ? Design Aids General Terms: Design, Performance

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
• Keywords: Accurate Hold Logic, DAC 2007, Design Automation, Hold Logic, Telescopic Units