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34
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DAC
2007
ACM
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Computer Architecture
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DAC 2007
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An Efficient Mechanism for Performance Optimization of Variable-Latency Designs
14 years 12 months ago
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cad63.cs.nthu.edu.tw
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...
Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgo...
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