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    Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)

    14 years 5 months ago
    Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
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    Aviral Shrivastava, Nikil D. Dutt
    claim paper
    Added 30 Jun 2010
    Updated 30 Jun 2010
    Type Conference
    Year 2004
    Where ASPDAC
    Authors Aviral Shrivastava, Nikil D. Dutt
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