ASPDAC 2004 - PDF Preprint Papers

ASPDAC 2004 Asia and South Pacific Design Automation Conference

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ASPDAC
2004
ACM

218views Hardware» more ASPDAC 2004»

A compressed frame buffer to reduce display power consumption in mobile systems

14 years 3 months ago

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Abstract-- Despite the limited power available in a batteryoperated hand-held device, a display system must still have an enough resolution and sufficient color depth to deliver th...

Hojun Shim, Naehyuck Chang, Massoud Pedram

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Id	Views	Title	Status

1	218	A compressed frame buffer to reduce display power consumption in mobile systems	claim
2	169	Design of real-time VGA 3-D image sensor using mixed-signal techniques	claim
3	158	Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures	claim
4	151	Combinatorial group testing methods for the BIST diagnosis problem
5	149	A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design	claim
6	148	Optimal planning for mesh-based power distribution	claim
7	145	Hierarchical random-walk algorithms for power grid analysis	claim
8	144	Verification of timed circuits with symbolic delays	claim
9	141	An approach for reducing dynamic power consumption in synchronous sequential digital designs	claim
10	132	A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications	claim
11	132	On handling arbitrary rectilinear shape constraint	claim
12	130	Automatic process migration of datapath hard IP libraries	claim
13	129	Instruction buffering exploration for low energy VLIWs with instruction clusters	claim
14	126	High-level area and power-up current estimation considering rich cell library	claim
15	123	Dynamic voltage scaling of periodic and aperiodic tasks in priority-driven systems	claim
16	120	Compiler based exploration of DSP energy savings by SIMD operations	claim
17	120	Temporal floorplanning using 3D-subTCG	claim
18	120	Efficient octilinear Steiner tree construction based on spanning graphs	claim
19	119	A fast congestion estimator for routing with bounded detours	claim
20	118	Fast and efficient voltage scheduling by evolutionary slack distribution	claim
21	118	Minimization of memory size for heterogeneous MDDs	claim
22	117	Performance-driven global placement via adaptive network characterization	claim
23	116	Temperature-aware global placement	claim
24	115	A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique	claim
25	114	Timing measurement unit with multi-stage TVC for embedded memories	claim
26	114	Layer assignment for crosstalk risk minimization	claim
27	113	Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction	claim
28	112	Longest path selection for delay test under process variation	claim
29	112	Efficient reachability checking using sequential SAT	claim
30	111	Gate delay calculation considering the crosstalk capacitances	claim
31	110	Embedded software generation from system level design languages	claim
32	109	Resource-constrained low-power bus encoding with crosstalk delay elimination	claim
33	109	Design methodology for IRA codes	claim
34	107	Interconnect capacitance estimation for FPGAs	claim
35	107	Minimization of the expected path length in BDDs based on local changes	claim
36	107	Fast, predictable and low energy memory references through architecture-aware compilation	claim
37	106	A novel memory size model for variable-mapping in system level design	claim
38	105	Improved symbolic simulation by functional-space decomposition	claim
39	104	A small-area high-performance 512-point 2-dimensional FFT single-chip processor	claim
40	103	Design and implementation of a secret key steganographic micro-architecture employing FPGA	claim
41	102	SPICE compatible circuit models for partial reluctance K	claim
42	102	TranGen: a SAT-based ATPG for path-oriented transition faults	claim
43	102	A dynamic element matching circuit for multi-bit delta-sigma modulators	claim
44	101	A sub-mW MPEG-4 motion estimation processor core for mobile video application	claim
45	98	Enabling on-chip diversity through architectural communication design	claim
46	97	Interconnect design methods for memory design	claim
47	97	A cosynthesis algorithm for application specific processors with heterogeneous datapaths	claim
48	97	Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost	claim
49	96	Register binding and port assignment for multiplexer optimization	claim
50	96	Rate analysis for streaming applications with on-chip buffer constraints	claim
51	96	Mixed-clock issue queue design for energy aware, high-performance cores	claim
52	95	Toward mobile phone Linux	claim
53	94	Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)	claim
54	94	Improving simulation-based verification by means of formal methods	claim
55	93	Layer assignment for reliable system-on-package	claim
56	92	Modeling of coplanar waveguide for buffered clock tree	claim
57	92	Analog circuit behavioral modeling via wavelet collocation method with auto-companding	claim
58	91	A 35 dB-linear exponential function generator for VGA and AGC applications	claim
59	91	Piecewise quadratic waveform matching with successive chord iteration	claim
60	89	Predictable design of low power systems by pre-implementation estimation and optimization	claim
61	88	A high performance bus communication architecture through bus splitting	claim
62	87	ShatterPB: symmetry-breaking for pseudo-Boolean formulas	claim
63	85	Integrating buffer planning with floorplanning for simultaneous multi-objective optimization	claim
64	85	Representative frequency for interconnect R(f)L(f)C extraction	claim
65	85	Multi-level placement with circuit schema based clustering in analog IC layouts	claim
66	84	Combining ordered best-first search with branch and bound for exact BDD minimization	claim
67	84	A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery	claim
68	84	Jitter spectral extraction for multi-gigahertz signal	claim
69	83	A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline	claim
70	83	Instruction set and functional unit synthesis for SIMD processor cores	claim
71	81	High-frequency noise in RF active CMOS mixers	claim
72	81	Technology mapping and packing for coarse-grained, anti-fuse based FPGAs	claim
73	80	Exploiting program execution phases to trade power and performance for media workload	claim
74	80	Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting	claim
75	79	Enhancing the performance of multi-cycle path analysis in an industrial setting	claim
76	79	Preserving synchronizing sequences of sequential circuits after retiming	claim
77	79	Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor	claim
78	79	NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO	claim
79	78	On compliance test of on-chip bus for SOC	claim
80	78	Automatic generation of bus functional models from transaction level models	claim
81	77	Design diagnosis using Boolean satisfiability	claim
82	76	Efficient computation of canonical form for Boolean matching in large libraries	claim
83	76	RF design methodologies bridging system-IC-module design	claim
84	76	A fast method to derive minimum SOPs for decomposable functions	claim
85	75	Power-performance trade-off using pipeline delays	claim
86	75	A thread partitioning algorithm in low power high-level synthesis	claim
87	74	Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming	claim
88	72	On mismatch in the deep sub-micron era - from physics to circuits	claim
89	72	Exploiting state encoding for invariant generation in induction-based property checking	claim
90	71	Golay and wavelet error control codes in VLSI	claim
91	70	Object-oriented modeling and synthesis of SystemC specifications	claim
92	65	MOSFET modeling for RF-CMOS design	claim

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