Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture

— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable hard Intellectual Property (IP) cores. Macro block-based physical design implementation needs to find a well balanced solution among chip area, on-chip communication energy and critical communication path delay. We present in this paper an automated way to implement an energy optimal netlist interconnecting the hard macro blocks using a heavily segmented communication architecture. We explore the entire trade-off curve among the network energy, chip area and critical communication path delay at the floorplanning stage based on two real-life application drivers. Large energy gains with small area overheads are illustrated during the floorplanning stage. This trade-off profile is a good guideline for the SOC designers to choose the optimal solution for their specific systems.

• Type: Conference
• Year: 2006
• Where: SLIP
• Authors: Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor
• Keywords: Chip Area, Communication Path Delay, Computer Networks, Critical Communication Path, SLIP 2006