Abstract--As demand increases for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used i...
—In this paper we present an architectural analysis of a smart DMA (sDMA) controller for protocol stack acceleration in mobile devices supporting 3GPP’s Long Term Evolution (LT...
Sebastian Hessel, David Szczesny, Felix Bruns, Att...
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...