Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)

As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essential to model these leakage effects properly. Moreover, typical microprocessor caches are pipelined to keep up with the speed of the processor, and the effects of pipelining overhead need to be properly accounted for. In this paper, we present a detailed study of pipelined nanometer caches with detailed energy/power dissipation breakdowns showing where and how the power is dissipated within a nanometer cache. We explore a three-dimensional pipelined cache design space that includes cache size (16kB to 512kB), cache associativity (directmapped to 16-way) and process technology (90nm, 65nm, 45nm and 32nm). Among our findings, we show that cache bitline leakage is increasingly becoming the dominant cause of power dissipation in nanometer technology nodes. We show that subthreshold leakage is the main cause of sta...

• Type: Conference
• Year: 2006
• Where: ISLPED
• Authors: Samuel Rodríguez, Bruce L. Jacob
• Keywords: Cache, ISLPED 2006, Nanometer Cache, Power Dissipation