HPCA
2011
IEEE
13 years 4 months ago
2011
IEEE
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
GLVLSI
2011
IEEE
13 years 4 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
DATE
2011
IEEE
13 years 4 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
TVLSI
2010
13 years 7 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
SIGOPS
2010
13 years 7 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
CAL
2010
13 years 9 months ago
2010
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
CAL
2010
13 years 10 months ago
2010
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
ICPP
2009
IEEE
13 years 10 months ago
2009
IEEE
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...