Energy/Power Estimation of Regular Processor Arrays

We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for implementations on FPGA based CO-processors. We focus on the respective impact of the array design parameters on the overall off-chip i/o traffic and the number and sizes of the local memories in the array. The model is validated experimentally and shows good results (12.7% RMS error in the predictions). Keywords Power Estimation, Programmable logic, Design Space Exploration, Processor Array Partitioning

• Type: Conference
• Year: 2002
• Where: ISSS
• Authors: Sanjay V. Rajopadhye, Steven Derrien
• Keywords: Array Design Parameters, Array Implementations, Hardware, ISSS 2002, Processor Array Partitioning