ISSS 2002 - PDF Preprint Papers

ISSS 2002 International Symposium on System Synthesis

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ISSS
2002
IEEE

194views Hardware» more ISSS 2002»

Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems

14 years 4 months ago

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This paper addresses the problem of mapping an application, which is highly dynamic in the future, onto a heterogeneous multiprocessor platform in an energy eﬃcient way. A two-p...

Rudy Lauwereins, Chun Wong, Paul Marchal, Johan Vo...

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Id	Views	Title	Status

1	194	Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems	claim
2	176	Controller Estimation for FPGA Target Architectures during High-Level Synthesis	claim
3	174	A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor	claim
4	154	Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops	claim
5	151	Tuning of Loop Cache Architectures to Programs in Embedded System Design	claim
6	148	A Case Study of Hardware and Software Synthesis in ForSyDe	claim
7	144	A Visual Approach to Validating System Level Designs	claim
8	142	Round-Robin Arbiter Design and Generation	claim
9	142	Energy/Power Estimation of Regular Processor Arrays	claim
10	141	An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems	claim
11	139	An Adaptive Low-Power Transmission Scheme for On-Chip Networks	claim
12	139	Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study	claim
13	138	An Object-Oriented Design Process for System-on-Chip Using UML	claim
14	136	Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors	claim
15	136	OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip Multiprocessors	claim
16	133	Efficient Simulation of Synthesis-Oriented System Level Designs	claim
17	133	Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems	claim
18	130	System-Level Modeling of a Network Switch SoC	claim
19	129	System-Level Design of IEEE1394 Bus Segment Bridge	claim
20	127	Validation in a Component-Based Design Flow for Multicore SoCs	claim
21	127	Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis	claim
22	126	Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design	claim
23	125	Security-Driven Exploration of Cryptography in DSP Cores	claim
24	125	Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification	claim
25	124	A New Performance Evaluation Approach for System Level Design Space Exploration	claim
26	124	Timing Analysis of Embedded Software for Speculative Processors	claim
27	120	Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs	claim
28	120	Optimal Message-Passing for Data Coherency in Distributed Architecture	claim
29	117	CMP on SoC: Architect's View	claim
30	111	System-Level Abstraction Semantics	claim
31	110	Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors	claim
32	109	System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory	claim
33	109	The Formal Execution Semantics of SpecC	claim
34	106	Modeling Assembly Instruction Timing in Superscalar Architectures	claim
35	106	Securing Wireless Data: System Architecture Challenges	claim
36	103	A Symbolic Approach for the Combined Solution of Scheduling and Allocation	claim
37	100	Code Compression for VLIW Processors Using Variable-to-Fixed Coding	claim
38	96	A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design	claim
39	95	Datapath Merging and Interconnection Sharing for Reconfigurable Architectures	claim
40	93	Low-Power Data Memory Communication for Application-Specific Embedded Processors	claim

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