An error-correcting unordered code and hardware support for robust asynchronous global communication

A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i.e., unordered) codes with the faulttolerance of error-correcting codes. The proposed errorcorrecting unordered (ECU) code, called Zero-Sum, can safely accommodate arbitrary skew in arrival times of individual bits in a packet, while simultaneously providing 1-bit correction and 2-bit detection. A systematic code is targeted, where data can be directly extracted from the codewords. A basic method for generating the code is presented, as well as detailed designs for the supporting hardware blocks. An outline of the system micro-architecture and its operating protocol is also given. When compared to the best previous systematic ECU code, the new code provides a 5.74 to 18.18% reduction in transition power for most field sizes, with better or comparable coding efficiency. Pre-layout technology-mapped implementa...

• Type: Conference
• Year: 2010
• Where: DATE
• Authors: Melinda Y. Agyekum, Steven M. Nowick
• Keywords: DATE 2010, Ecu Codes, Hardware, Non-systematic Ecu Codes, Systematic Ecu Code