Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures

With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism (ILP) in applications has gone up considerably. However, monolithic register file VLIW architectures present scalability problems due to a centralized register file which is far slower than the functional units (FU). Clustered VLIW architectures, with a subset of FUs connected to any RF are the solution to this scalability problem. Recent studies with a wide variety of inter-cluster interconnection mechanisms have presented substantial gains in performance (number of cycles) over the most studied RFto-RF type interconnections. However, these studies have compared only one or two design points in the RF-to-RF interconnects design space. In this paper, we extend the previous reported work. We consider both multi-cycle and pipelined buses. To obtain realistic bus latencies, we synthesized the various architec...

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
• Keywords: DATE 2005, Hardware, Pipelined Buses, VLIW Architectures, file Vliw Architectures