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DATE
2005
IEEE

278views Hardware» more DATE 2005»

Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation

14 years 5 months ago

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Designers of factory automation applications increasingly demand for tools for rapid prototyping of hardware extensions to existing systems and veriﬁcation of resulting behavior...

Franco Fummi, Mirko Loghi, Stefano Martini, Marco ...

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Id	Views	Title	Status

1	278	Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation	claim
2	235	Challenges in Embedded Memory Design and Test	claim
3	224	Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL	claim
4	204	Evaluation of Error-Resilience for Reliable Compression of Test Data	claim
5	197	picoArray Technology: The Tool's Story	claim
6	192	C Based Hardware Design for Wireless Applications	claim
7	187	Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs	claim
8	180	A Coprocessor for Accelerating Visual Information Processing	claim
9	176	A Synthesizable IP Core for DVB-S2 LDPC Code Decoding	claim
10	176	Effective Lower Bounding Techniques for Pseudo-Boolean Optimization	claim
11	176	LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks	claim
12	172	Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development	claim
13	172	Evolutionary Optimization in Code-Based Test Compression	claim
14	171	Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems	claim
15	169	Optimized Generation of Data-Path from C Codes for FPGAs	claim
16	169	Activity Packing in FPGAs for Leakage Power Reduction	claim
17	169	Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies	claim
18	169	Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems	claim
19	168	Hardware Acceleration of Hidden Markov Model Decoding for Person Detection	claim
20	167	A New Task Model for Streaming Applications and Its Schedulability Analysis	claim
21	165	Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture	claim
22	165	AutoMoDe - Model-Based Development of Automotive Software	claim
23	164	Automated Synthesis of Assertion Monitors using Visual Specifications	claim
24	164	Automotive System Design - Challenges and Potential	claim
25	164	Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture	claim
26	163	A Hardware-Friendly Wavelet Entropy Codec for Scalable Video	claim
27	162	A Model-Based Approach for Executable Specifications on Reconfigurable Hardware	claim
28	160	SOC Testing Methodology and Practice	claim
29	159	HEBS: Histogram Equalization for Backlight Scaling	claim
30	158	The Challenges of Hardware Synthesis from C-Like Languages	claim
31	158	Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits	claim
32	158	Scheduling of Soft Real-Time Systems for Context-Aware Applications	claim
33	155	RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC	claim
34	155	Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing	claim
35	154	Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring	claim
36	154	A Time Slice Based Scheduler Model for System Level Design	claim
37	154	Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit	claim
38	153	Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices	claim
39	152	Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips	claim
40	152	Modeling and Propagation of Noisy Waveforms in Static Timing Analysis	claim
41	151	Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications	claim
42	150	Pueblo: A Modern Pseudo-Boolean SAT Solver	claim
43	149	A Public-Key Watermarking Technique for IP Designs	claim
44	148	A Dependability-Driven System-Level Design Approach for Embedded Systems	claim
45	148	On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits	claim
46	147	Buffer Insertion Considering Process Variation	claim
47	146	Wireless LAN: Past, Present, and Future	claim
48	146	Nonuniform Banking for Reducing Memory Energy Consumption	claim
49	144	An Accurate SER Estimation Method Based on Propagation Probability	claim
50	144	Context Sensitive Performance Analysis of Automotive Applications	claim
51	143	galsC: A Language for Event-Driven Embedded Systems	claim
52	143	Q-DPM: An Efficient Model-Free Dynamic Power Management Technique	claim
53	143	Energy Bounds for Fault-Tolerant Nanoscale Designs	claim
54	143	Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies	claim
55	141	Multimedia Applications of Multiprocessor Systems-on-Chips	claim
56	140	Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction	claim
57	140	Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing	claim
58	139	EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation	claim
59	139	Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model	claim
60	138	BB-GC: Basic-Block Level Garbage Collection	claim
61	136	Increasing Register File Immunity to Transient Errors	claim
62	135	Compositional Memory Systems for Multimedia Communicating Tasks	claim
63	134	Assertion-Based Design Exploration of DVS in Network Processor Architectures	claim
64	133	Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access	claim
65	133	Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?	claim
66	133	Locality-Aware Process Scheduling for Embedded MPSoCs	claim
67	133	A Real-Time Streaming Memory Controller	claim
68	132	Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage	claim
69	132	Statistical Timing Analysis using Levelized Covariance Propagation	claim
70	132	An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories	claim
71	131	Unified Modeling of Complex Real-Time Control Systems	claim
72	131	Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions	claim
73	130	Design for Verification of SystemC Transaction Level Models	claim
74	129	Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications	claim
75	129	Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling	claim
76	128	Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits	claim
77	128	On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs	claim
78	128	Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction	claim
79	128	Design of a Virtual Component Neutral Network-on-Chip Transaction Layer	claim
80	127	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application	claim
81	127	Quantum Circuit Simplification Using Templates	claim
82	127	Design Space Exploration for Dynamically Reconfigurable Architectures	claim
83	126	An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories	claim
84	126	The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits	claim
85	125	Hybrid BIST Based on Repeating Sequences and Cluster Analysis	claim
86	125	Hardware Engines for Bus Encryption: A Survey of Existing Techniques	claim
87	125	Thermal-Aware Task Allocation and Scheduling for Embedded Systems	claim
88	125	Cantilever-Based Biosensors in CMOS Technology	claim
89	125	Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler	claim
90	125	An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs	claim
91	124	Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis	claim
92	123	Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling	claim
93	123	Low Power Oriented CMOS Circuit Optimization Protocol	claim
94	123	An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor	claim
95	123	Defining an Enhanced RTL Semantics	claim
96	122	Direct Conversion Pulsed UWB Transceiver Architecture	claim
97	122	Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization	claim
98	122	Systematic Transaction Level Modeling of Embedded Systems with SystemC	claim
99	122	Applying UML and MDA to Real Systems Design	claim
100	122	Diagnostic and Detection Fault Collapsing for Multiple Output Circuits	claim
101	122	A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs	claim
102	121	Joint Power Management of Memory and Disk	claim
103	121	C Compiler Retargeting Based on Instruction Semantics Models	claim
104	121	Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits	claim
105	121	Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization	claim
106	120	Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints	claim
107	120	Why Systems-on-Chip Needs More UML like a Hole in the Head	claim
108	120	Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance	claim
109	119	Functional Validation of System Level Static Scheduling	claim
110	119	On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips	claim
111	119	UML 2.0 Profile for Embedded System Design	claim
112	119	Integrated Electronics in the Car and the Design Chain Evolution or Revolution?	claim
113	119	A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs	claim
114	118	Realization of a Virtual Lambda Sensor on a Fixed Precision System	claim
115	118	An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms	claim
116	118	A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems	claim
117	118	Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach	claim
118	117	Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory	claim
119	117	Implicit and Exact Path Delay Fault Grading in Sequential Circuits	claim
120	117	Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs	claim
121	117	Low Cost Task Migration Initiation in a Heterogeneous MP-SoC	claim
122	117	A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs	claim
123	117	Power Saving Techniques for Wireless LANs	claim
124	117	A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips	claim
125	116	A Complete Network-On-Chip Emulation Framework	claim
126	116	FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations	claim
127	116	Uniformly-Switching Logic for Cryptographic Hardware	claim
128	116	Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition	claim
129	116	FPGA based Agile Algorithm-On-Demand Co-Processor	claim
130	115	Stochastic Power Grid Analysis Considering Process Variations	claim
131	115	Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission	claim
132	115	A New Embedded Measurement Structure for eDRAM Capacitor	claim
133	115	An Efficient Sequential SAT Solver With Improved Search Strategies	claim
134	115	Functional Coverage Driven Test Generation for Validation of Pipelined Processors	claim
135	115	An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs	claim
136	115	Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach	claim
137	114	A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling	claim
138	113	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures	claim
139	113	Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection	claim
140	112	Platform Based Design for Automotive Sensor Conditioning	claim
141	112	TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques	claim
142	112	Simultaneous Reduction of Dynamic and Static Power in Scan Structures	claim
143	111	Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures	claim
144	111	MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption	claim
145	110	Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture	claim
146	110	Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters	claim
147	110	Software Thread Integration and Synthesis for Real-Time Applications	claim
148	110	LC Oscillator Driver for Safety Critical Applications	claim
149	110	Embedded Automotive System Development Process	claim
150	110	Rapid Generation of Thermal-Safe Test Schedules	claim
151	110	Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration	claim
152	109	ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement	claim
153	109	Design Method for Constant Power Consumption of Differential Logic Circuits	claim
154	109	Systematic Analysis of Active Clock Deskewing Systems Using Control Theory	claim
155	108	Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination	claim
156	108	A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks	claim
157	107	Fine Grain QoS Control for Multimedia Application Software	claim
158	107	On Statistical Timing Analysis with Inter- and Intra-Die Variations	claim
159	107	Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique	claim
160	107	Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores	claim
161	106	SAT-Based Complete Don't-Care Computation for Network Optimization	claim
162	105	A Novel Unified Architecture for Public-Key Cryptography	claim
163	105	Mutation Sampling Technique for the Generation of Structural Test Data	claim
164	105	An Improved Multi-Level Framework for Force-Directed Placement	claim
165	104	Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces	claim
166	104	Queue Management in Network Processors	claim
167	104	A SoC Design Methodology Involving a UML 2.0 Profile for SystemC	claim
168	104	Defect Aware Test Patterns	claim
169	103	Noise Figure Evaluation Using Low Cost BIST	claim
170	102	Statistical Timing Based Optimization using Gate Sizing	claim
171	102	New Schemes for Self-Testing RAM	claim
172	102	Considering Circuit Observability Don't Cares in CNF Satisfiability	claim
173	102	Modeling of a Reconfigurable OFDM IP Block Family For an RF System Simulator	claim
174	102	Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach	claim
175	102	Lifetime Modeling of a Sensor Network	claim
176	101	TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform	claim
177	101	Compiler-Directed Instruction Duplication for Soft Error Detection	claim
178	101	Techniques for Fast Transient Fault Grading Based on Autonomous Emulation	claim
179	101	New Perspectives and Opportunities From the Wild West of Microelectronic Biochips	claim
180	100	DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement	claim
181	100	Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis	claim
182	100	Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis	claim
183	100	UML 2.0 - Overview and Perspectives in SoC Design	claim
184	100	OS Debugging Method Using a Lightweight Virtual Machine Monitor	claim
185	100	The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application	claim
186	99	A New System Design Methodology for Wire Pipelined SoC	claim
187	99	Verification of Embedded Memory Systems using Efficient Memory Modeling	claim
188	99	Symmetric Multiprocessing on Programmable Chips Made Easy	claim
189	99	A Network Traffic Generator Model for Fast Network-on-Chip Simulation	claim
190	99	Worst-Case and Average-Case Analysis of n-Detection Test Sets	claim
191	99	Leakage-Aware Interconnect for On-Chip Network	claim
192	99	UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design	claim
193	98	Hardware Accelerated Power Estimation	claim
194	98	Space-Efficient Bounded Model Checking	claim
195	98	A High Quality/Low Computational Cost Technique for Block Matching Motion Estimation	claim
196	98	Memory Testing Under Different Stress Conditions: An Industrial Evaluation	claim
197	97	Specification Test Compaction for Analog Circuits and MEMS	claim
198	97	Synchronization Processor Synthesis for Latency Insensitive Systems	claim
199	97	Efficient Solution of Language Equations Using Partitioned Representations	claim
200	96	Framework for Fault Analysis and Test Generation in DRAMs	claim
201	96	Systematic Figure of Merit Computation for the Design of Pipeline ADC	claim
202	96	Reliable System Specification for Self-Checking Data-Paths	claim
203	96	eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical Detection	claim
204	96	Structural Testing Based on Minimum Kernels	claim
205	96	DVS for On-Chip Bus Designs Based on Timing Error Correction	claim
206	96	Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip	claim
207	94	Automatic Formal Verification of Fused-Multiply-Add FPUs	claim
208	94	Meeting the Embedded Design Needs of Automotive Applications	claim
209	94	A New Approach to Component Testing	claim
210	93	Reconfigurable Elliptic Curve Cryptosystems on a Chip	claim
211	93	Model Reuse through Hardware Design Patterns	claim
212	93	A Faster Counterexample Minimization Algorithm Based on Refutation Analysis	claim
213	91	Reliability-Centric High-Level Synthesis	claim
214	90	System Level Analysis of the Bluetooth Standard	claim
215	89	Integration, Verification and Layout of a Complex Multimedia SOC	claim
216	88	System Synthesis for Networks of Programmable Blocks	claim
217	87	Concurrent Error Detection in Asynchronous Burst-Mode Controllers	claim
218	84	Tag Overflow Buffering: An Energy-Efficient Cache Architecture	claim
219	84	Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation	claim
220	84	A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms	claim
221	83	At-Speed Logic BIST for IP Cores	claim
222	82	Energy-Aware Routing for E-Textile Applications	claim

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