Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing

Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary faultrecovery systems should benefit by accommodating routing. In this paper, we propose an evolutionary fault-recovery system employing a genetic representation that takes into account both logic and routing configurations. Experiments were run using a software model of the Xilinx Virtex FPGA. We report that using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuck-at-zero fault. Evolutionary experiments with the hardware in the loop have begun and we discuss the preliminary results.

• Type: Conference
• Year: 2003
• Where: IPPS
• Authors: Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMara
• Keywords: Distributed And Parallel Computing, Evolutionary, IPPS 2003, Most Evolutionary Approaches, Virtex Combinational Logic