Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs

The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several independent LUTs of two di erent sizes called ICLBs. The Actel ES6500 family is an example of a class of commercially available ICLBs. Given a tree network with n nodes, the only previously known approach for minimum area tree-based mapping to ICLBs was a heuristic with running time nd+1 , where d is the maximum indegree of any node. We give an On3 time exact algorithm for mapping a given tree network, an improvement over this heuristic in terms of run time and the solution quality. For general networks, an e ective strategy is to break it into trees and combine them. We also give an On3 exact algorithm for combining the optimal solutions to these trees, under the condition that LUTs do not go across trees. The method can be extended to solve mapping onto CLBs that can be con gured into di erent ICLBs, e.g. ...

• Type: Conference
• Year: 1998
• Where: DAC
• Authors: Madhukar R. Korupolu, K. K. Lee, D. F. Wong
• Keywords: Area Tree-based Mapping, DAC 1998, Design Automation, Di Erent Sizes, Time Exact Algorithm