Express Cube Topologies for on-Chip Interconnects

Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. Scalability of on-chip interconnect topologies is critical to meeting these demands. In this work, we seek to develop a better understanding of how network topologies scale with regard to cost, performance, and energy considering the advantages and limitations afforded on a die. Our contributions are three-fold. First, we propose a new topology, called Multidrop Express Channels (MECS), that uses a one-to-many communication model enabling a high degree of connectivity in a bandwidth-efficient manner. In a 64-terminal network, MECS enjoys a 9% latency advantage over other topologies at low network loads, which extends to over 20% in a 256terminal network. Second, we demonstrate that partitioning the available wires among multiple networks and channels enables new opportunities for trading-off performance, area...

• Type: Conference
• Year: 2009
• Where: HPCA
• Authors: Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu
• Keywords: Computer Architecture, HPCA 2009, Multidrop Express Channels, Network Topologies, On-chip Interconnect Topologies