A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks

As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been identified to be a major design challenge. Network topologies have high impact on network power consumption. Technology scaling is another important factor that affects network power since each new technology changes semiconductor physical properties. As shown in this paper, these two aspects need to be considered synergistically. In this paper, we characterize the impact of process technologies on network energy for a range of topologies, starting from 2-dimensional meshes/tori, to variants of meshes/tori that incorporate higher dimensions, multiple hierarchies and express channels. We present a method which uses an analytical model to predict the most energy-efficient topology based on network size and architecture parameters for future technologies. Our model is validated against cycle-accurate network powe...

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
• Keywords: DATE 2005, Hardware, Network Power, Network Power Consumption, Power Consumption