Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis

The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suitable for evaluation by conventional gate-level simulators and hardware simulation accelerators. TRANALYZE has the same generality and accuracy as switch-level simulation, generating models for a wide range of technologies and design styles, while expressing the detailed effects of bidirectional transistors, stored charge, and multiple signal strengths. It produces models with size comparable to ones generated by hand.

• Type: Conference
• Year: 1991
• Where: ICCAD
• Authors: Randal E. Bryant
• Keywords: Delay Logic Primitives, Hardware, Hardware Simulation Accelerators, ICCAD 1991, MOS Transistor Circuit