Factoring logic functions using graph partitioning

Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical properties and the dependent stage where mapping to a physical cell library is done. The independent stage includes logic operations like Decomposition, Extraction, Factoring, Substitution and Elimination. These operations are done with some kind of division (boolean, algebraic), with the goal being to obtain a logically equivalent factored form which minimizes the number of literals. In this paper, we present an algorithm for factoring that uses graph partitioning rather than division. Central to our approach is to combine this with the use of special classes of boolean functions, such as read-once functions, to devise new combinatorial algorithms for logic minimization. Our method has been implemented in the SIS environment, and an empirical evaluation indicates that we usually get significantly better resul...

• Type: Conference
• Year: 1999
• Where: ICCAD
• Authors: Martin Charles Golumbic, Aviad Mintz
• Keywords: Algorithmic Logic Synthesis, Hardware, ICCAD 1999, Independent Stage, Logic Minimization