ICCAD 1999 - PDF Preprint Papers

ICCAD 1999 International Conference on Computer-Aided Design

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ICCAD
1999
IEEE

181views Hardware» more ICCAD 1999»

A new heuristic for rectilinear Steiner trees

14 years 3 months ago

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The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NP-hard, and much work has been ...

Ion I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganle...

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Id	Views	Title	Status

1	181	A new heuristic for rectilinear Steiner trees	claim
2	153	Cycle time and slack optimization for VLSI-chips	claim
3	148	SAT based ATPG using fast justification and propagation in the implication graph	claim
4	132	The associative-skew clock routing problem	claim
5	125	Direct synthesis of timed asynchronous circuits	claim
6	120	Regularity extraction via clan-based structural circuit decomposition	claim
7	120	Design and optimization of LC oscillators	claim
8	119	Factoring logic functions using graph partitioning	claim
9	115	Fast performance analysis of bus-based system-on-chip communication architectures	claim
10	115	An approach for improving the levels of compaction achieved by vector omission	claim
11	113	Attractor-repeller approach for global placement	claim
12	109	Transient sensitivity computation for transistor level analysis and tuning	claim
13	109	Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis	claim
14	108	Copy detection for intellectual property protection of VLSI designs	claim
15	105	Noise analysis of non-autonomous radio frequency circuits	claim
16	101	Efficient model reduction of interconnect via approximate system gramians	claim
17	99	Concurrent logic restructuring and placement for timing closure	claim
18	99	FunState - an internal design representation for codesign	claim
19	98	Buffer block planning for interconnect-driven floorplanning	claim
20	97	A methodology for correct-by-construction latency insensitive design	claim
21	96	Implication graph based domino logic synthesis	claim
22	95	Dynamic power management using adaptive learning tree	claim
23	94	Function inlining under code size constraints for embedded processors	claim
24	93	Interconnect parasitic extraction in the digital IC design methodology	claim
25	93	LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay	claim
26	92	Interface and cache power exploration for core-based embedded system design	claim
27	92	Implicit enumeration of strongly connected components	claim
28	90	An implicit connection graph maze routing algorithm for ECO routing	claim
29	90	Marsh: min-area retiming with setup and hold constraints	claim
30	89	A bipartition-codec architecture to reduce power in pipelined circuits	claim
31	88	Performance optimization under rise and fall parameters	claim
32	87	Repeater insertion in tree structured inductive interconnect	claim
33	86	Clock skew scheduling for improved reliability via quadratic programming	claim
34	86	A framework for testing core-based systems-on-a-chip	claim
35	84	Improving coverage analysis and test generation for large designs	claim
36	84	A clustering- and probability-based approach for time-multiplexed FPGA partitioning	claim
37	84	Synthesis of asynchronous control circuits with automatically generated relative timing assumptions	claim
38	84	OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic	claim
39	84	Power minimization using system-level partitioning of applications with quality of service requirements	claim
40	84	Timing-driven partitioning for two-phase domino and mixed static/domino implementations	claim
41	82	Fault modeling and simulation for crosstalk in system-on-chip interconnects	claim
42	81	Analytical macromodeling for high-level power estimation	claim
43	81	Robust optimization based backtrace method for analog circuits	claim
44	81	A novel design methodology for high performance and low power digital filters	claim
45	81	Modeling design constraints and biasing in simulation using BDDs	claim
46	80	Lower bound on latency for VLIW ASIP datapaths	claim
47	80	What is the cost of delay insensitivity?	claim
48	79	Improved interconnect sharing by identity operation insertion	claim
49	79	A wide frequency range surface integral formulation for 3-D RLC extraction	claim
50	78	Interconnect scaling implications for CAD	claim
51	78	Probabilistic state space search	claim
52	77	Synthesis for multiple input wires replacement of a gate for wiring consideration	claim
53	77	Virtual screening: a step towards a sparse partial inductance matrix	claim
54	77	Symbolic functional and timing verification of transistor-level circuits	claim
55	76	Optimal allocation of carry-save-adders in arithmetic optimization	claim
56	75	Functional timing optimization	claim
57	74	Lazy group sifting for efficient symbolic state traversal of FSMs	claim
58	72	An integrated algorithm for combined placement and libraryless technology mapping	claim
59	72	Validation and test generation for oscillatory noise in VLSI interconnects	claim
60	71	Localized watermarking: methodology and application to operation scheduling	claim
61	71	Partial BIST insertion to eliminate data correlation	claim
62	68	Throughput optimization of general non-linear computations	claim
63	67	Realizable reduction for RC interconnect circuits	claim
64	66	Test scheduling for core-based systems	claim
65	66	Timing-safe false path removal for combinational modules	claim
66	62	A scalable substrate noise coupling model for mixed-signal ICs	claim
67	59	Parameterized RTL power models for combinational soft macros	claim
68	57	Least fixpoint approximations for reachability analysis	claim
69	54	Synchronous equivalence for embedded systems: a tool for design exploration	claim

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